1. Field
The embodiments are generally directed to data verification using redundant computations, and more specifically to data verification using hardware-based redundant computations.
2. Background Art
There are several approaches to data verification through fault tolerance, in particular information redundancy, spatial redundancy and temporal redundancy. Information redundancy uses coding techniques, such as parity and error correction codes to detect and recover from data errors. Spatial redundancy duplicates the hardware that requires protection. Temporal redundancy involves replicating computations and running the replicated computations on the same hardware.
Fault tolerance through redundant computation may be used in central processing units (“CPUs”). However, redundant computations on the CPUs impose significant performance overhead due to CPUs' limited ability to process data in parallel.
Some redundant execution may occur on the graphics processing units (“GPUs”). For example, adjacent single instruction multiple data lanes (“SIMD” lanes) may be replicated in hardware and their outputs compared prior to the output being updated in the system memory.